The invention relates to the development of two discrete devices constructed with BCDV technology, that is, a step-down switching voltage regulator and a current loop for a battery charger. Reference will be made to this field of application in the ensuing description for convenience of explanation. Switching voltage regulators are extensively employed in many applications because of their effectiveness and accuracy. The basic components of these regulators include a power switch, a loop-back diode, an LC output filter, and an optional current sensor for the battery charger.
To compete favorably, new generation regulators exhibit ever higher switching frequencies so that smaller external components can be used, both for economy of circuit area and of cost. In particular, regulators of this type preferably have the smallest possible number of external components. An increased frequency results in the regulator efficiency being limited mainly by the commutation losses of the power switch. Accordingly, one critical design aspect of such regulators concerns the driver circuit portion of the power switch, since commutation losses are dependent on that portion.
Commercially available regulators typically use an N-channel MOS transistor for a power switch because of the simple way in which these switches can be driven. However, to ensure adequate overdrive for the driver, a MOS power switch requires a higher drive voltage than the supply voltage for the device. A boosted voltage may be provided basically in one of two ways, namely by using a charge pump or by using a bootstrap capacitor. Yet, both of these solutions have drawbacks. In particular, the former requires substantial silicon area for its implementation in order for the charge pump to deliver the large currents needed to drive the power switch. In addition, one or more external capacitors are usually required. The second solution additionally requires an external component, i.e., a bootstrap capacitor, and circuitry to monitor the charging of the component to ensure full operability of the system in all running conditions. Furthermore, both solutions involve increased manufacturing costs for the switching regulator.
In an attempt to overcome these drawbacks and to lower manufacturing costs, P-channel MOS transistors have been used as power switches in late generation regulators. Unlike N-channel switches, these switches require no boost drive voltage and, therefore, no additional external components for the drive circuitry. A driver circuit adapted for these types of PMOS switches preferably exhibits the following features: ensuring fast turn-on/off edges, but without straining the loop-back diode and the switch itself; minimizing electromagnetic noise; preventing false operation of any current limiters active when turning on; and optimizing the regulator efficiency and exhibiting low static consumption.
In the prior art, the above features have been optimized for driving switches of the NMOS type. For example, U.S. Pat. No. 5,883,505, which is assigned to the present Assignee, discloses a driver circuit for an NMOS switch which can manage a loop-back diode in a smart style with good resultant drive. For sake of completeness, it should also be noted that the application of a higher drive voltage than a predetermined safe threshold across the gate and source terminals of the PMOS transistor should be avoided as the switch is turned on.
This specific problem has been the subject of extensive research and implementations directed in essentially three different ways. In a first of such attempts to address the problem, external switches are used which can withstand a drive voltage between their gate and source that is the same as the supply voltage to the device. In a second of such attempts, the maximum supply voltage (VALmax) is limited to a value lower than or equal to the maximum Vgsmax that the PMOS transistor can withstand without deterioration of its performance. In the third of such attempts, protection circuits are used incidental on the maximum supply voltage VALmax and still exceeding the gate-source voltage drop that the transistor can withstand.
An electric diagram of a conventional switching regulator which incorporates a PMOS power transistor equipped with a driver circuit including a protection circuit is shown in FIG. 3. The operation of the protection circuit causes very high consumption that markedly decreases the regulator efficiency. For example, in the case shown in FIG. 4, different current signals appearing in a conventional voltage regulator with a PMOS switch are plotted vs. time. Upon the leading edge of the turn-on signal DRIVE, three other signals ON1, ON2 and ON3 of predetermined duration are activated. These signals enable the power transistor to be turned on at a fast rate, while also overcoming a problem of recovery time with the loop-back diode. More particularly, the signal ON1 sets the current value I1, which makes the power transistor conductive. The signal ON2 further charges the gate of the power transistor with a current I2 over a time interval T2 during the reversal period of the loop-back diode.
Upon the leading edge of the signal DRAIN, the signal ON3 also becomes activated to bring the current on the gate terminal of the power transistor to a value I3 to quicken the transistor turn-on. Turning off presents no special problems, since a desired rate of turn-off can be simply achieved by suitable selection of a magnitude for a current Ioff. At the end of the turn-on transient, the current being delivered to the gate terminal of the power transistor should be larger than the current Ioff and the current supplied to the protection circuit. Designating T4 the turn-on time interval, it is I4=ION&gt;Ioff+Iclamp. This current is on the order of a few tens of mA and represents a substantial consumption. Reducing this consumption by limiting the drive currents is not feasible because the on/off transients would then be slowed and commutation losses increased.
Furthermore, during the time interval T3 (to be selected at the designing stage, and being subject to process spread and power supply variability), the power transistor gate is pulled down quite rapidly (T3 being on the order of a few tens of ns). The protection circuit will have a trigger time .DELTA.T when the gate keeps dropping to values well beyond the threshold Vgsmax. This has two drawbacks. First, such behavior may result in short term reliability problems because the power transistor gate is subjected to a higher voltage than is acceptable during the periods .DELTA.T. Secondly, to ensure a fast recovery, the protection circuit delivers a large amount of current, which further increases consumption.